1. Field of Invention
The inventions described and claimed relate in general to powering semiconductor devices. More specifically, they relate to internal voltage generating arrangements.
2. General Background and Related Art
Generally, it is desirable to operate portable electronic devices at as low a power consumption level as possible. In fact, power consumption level is probably one of the most competitive issues among manufacturers of portable electronic devices, semiconductor memory devices, etc. To minimize power consumption, it is helpful to operate semiconductor devices as voltages lower than those of externally supplied voltages. Therefore, an internal power voltage, lower than an externally supplied power voltage, is generated and used to operate semiconductor devices.
Because the power consumption of a CMOS circuit is proportional to square of voltage, power consumption can be reduced significantly, if the internal power voltage can be lowered. It is particularly helpful when the internal voltage source can be set and maintained to a static voltage. When this can be accomplished the operation of the chip is stable because the operational voltage is stable even when the external power voltage has some variation.
The semiconductor chip should operate normally (e.g., has constant access time) even when the external power voltage varies by 10%. This requirement can lead to circuit complexity. If a stable power source could be provided by an internal voltage generating apparatus, circuit design can be made simpler, which has many design advantages. For this reason, the concept of using an internal voltage generating apparatus was introduced.
FIG. 1 (Prior Art) is a circuit diagram of a conventional internal voltage generating apparatus. It includes a reference potential generating unit 100 for generating a reference voltage VREF1 having a predetermined potential level. A potential amplifying unit 200 amplifies the reference voltage VREF1. A reference potential converting unit 300 converts the potential of the reference voltage VREF1 by comparing a bias voltage VBIAS generated at a power voltage detector 10 with an output voltage VREF1_AMF from the potential amplifying unit 200. A driver unit 400 supplies a second reference voltage VREF2 converted at the reference potential converting unit 300 to a DRAM internal circuit 500 as an operational voltage in each of a standby mode and an active mode. The reference potential generating unit 100 is typically implemented by a Widlar Current Mirror which is well known in the art and its detailed description is omitted.
The potential amplifying unit 200 includes a comparator 1 receiving the reference voltage VREF1 at one of its two inputs. A PMOS transistor MP1 is coupled between a power voltage input Vcc and an output N1. Transistor MP1 has a gate coupled to the output of comparator 1. Two resistors R1 and R2 are serially coupled between the output N1 and ground for providing a feedback potential signal VA, resulting from voltage division based on the ratio of resistors R1 and R2, to the other one of the two inputs of the comparator 1.
The reference potential converting unit 300 includes a comparator 3 receiving the output potential VREF1_AMF from the potential amplifying unit 200 at one of its two inputs and a current sink ground voltage at the other one of its two inputs. A comparator 5 receives the bias voltage from the power voltage detector 10 at one of its two inputs. The other input of comparator 5 is coupled to a current sink ground voltage. Two PMOS transistors MP2 and MP3 are coupled in parallel to each other between the power voltage input Vcc and the current sink output N2. A gate of PMOS transistor MP2 is coupled to the output of the comparator 3 and a gate of PMOS transistor MP3 is coupled to the output of the comparator 5.
Driver unit 400 includes a standby driver 20 and an active driver 30. Drivers 20 and 30 are voltage followers that supply an operational voltage corresponding to the second reference voltage VREF2 in for standby mode and active mode, respectively. Drivers 20 and 30 include comparators 7 and 9, respectively, each receiving the second reference voltage VREF2 at ones of their two inputs and the current sink ground voltage at their other inputs, respectively. Two PMOS transistors MP4 and MP5 are coupled respectively between the power voltage input Vcc and the current sink output N2. A gate of PMOS transistor MP4 is coupled to the output of comparator 7 and a gate of PMOS transistor MP5 is coupled to the output of the comparator 9. The internal power voltage VINT1 is applied to the DRAM internal circuit 500 through a common drain of the two PMOS transistors MP4 and MP5.
The DRAM internal circuit 500 can be divided roughly into the core circuit block, i.e., a memory cell block, and the peripheral circuit block. In order to improve reliability of the memory cell, it is required that the operational voltage of the core circuit block is set to be low by supplying the core circuit block with a power voltage lower than the power voltage of the peripheral circuit block.
However, as will be appreciated referring to an output waveform of the internal voltage shown in FIG. 2 (Prior Art), the conventional internal voltage generating apparatus generates a single internal voltage VINT1 by using a single voltage drop circuit, which leads some operational difficulties.
Firstly, due to the internal power voltage being a single potential level, operational current value To determined by (Cpxc3x97VINT1+Ccxc3x97VINT1)xc3x97freq and subsequently memory core current increased. Accordingly, over-current flows through a cell capacitor and a swing voltage and a gate voltage of the cell increase. This voltage increase is bad for power consumption as well as in the cell reliability.
Furthermore, a noise characteristic of a circuit so powered deteriorates due to mutual noise interference of the core circuit block and the peripheral circuit block.
With this background in mind, the claimed inventions feature, at least in part a dual internal voltage generating arrangement. The voltage generating arrangements presented herein generate internal power voltages used respectively as operational voltages for 1) a peripheral circuit block and 2) a core circuit block of a memory chip. This allows for the operational voltage of the cell used for core to be a lower and stable level.
One exemplary embodiment of the inventions includes a dual internal voltage generating apparatus. A reference potential generating unit generates a reference voltage VREF1 of a predetermined potential level. First and second potential amplifying units, parallel to each other, amplify the reference voltage VREF1. A first reference potential converting unit converts the reference voltage to a first potential level by comparing a first bias voltage generated at a corresponding power voltage detector with the output voltage from the first potential amplifying unit. A second reference potential converting unit converts the reference voltage to a second potential level by comparing a second bias voltage generated at a corresponding power voltage detector with the output voltage from the second potential amplifying unit. A first driver unit receives the reference voltage generated at the first reference potential converting unit for generating a first internal voltage to be supplied to a peripheral circuit unit within a DRAM. A second driver unit receives the reference voltage generated at the second reference potential converting unit for generating a second internal voltage to be supplied to a core circuit unit within the DRAM.